LOW-COST SCALABLE SWITCHING SOLUTIONS FOR BROAD-BAND NETWORKING - THEATLANTA ARCHITECTURE AND CHIPSET

The ATLANTA(TM) switching architecture described in this article has t he following distinguishing characteristics: 1) is nonblocking, 2) sca les modularly over a wide range of switching and buffering capacities using commonly available implementation technology, 3) achieves high b uffer utilization while using distributed buffers, 4) has low complexi ty, and 5) provides a clear path for future growth in features. The AT LANTA architecture uses an innovative structure with ingress and egres s buffers, where selective backpressure is applied from the fabric to the ingress cards. Selective backpressure makes the buffers in the ing ress cards act as an extension of the output buffers in the fabric, ac hieving ''sharing'' of the distributed buffers and buffer utilization comparable with a centralized shared-memory switch. The advantage is t hat the majority of the buffers are in the ingress and egress port car ds, and are implemented using low-cost off-the-shelf memories regardle ss of the total switching capacity. Different arrangements are possibl e for the switch fabric. In the smallest configuration, the fabric con sists of a single standalone switching module; for larger switching ca pacities, the fabric is a modular three-stage memory/space/memory (MSM ) arrangement. The ATLANTA architecture provides optimal support of mu lticast traffic. The ATLANTA chipset provides the complete set of buil ding blocks for implementing ATM switches ranging in capacity from 622 Mb/s to 25 Gb/s. The chipset consists of four chips, two devices to b e used in the fabric and two in the port cards. The port devices provi de full-duplex inqress and egress functionality at 622 Mb/s port rate (plus the overhead due to the local header used internally to the swit ch). The physical interface to the incoming/outgoing lines supports th e UTOPIA II multiplexing standard, and the port devices manage multipl exing/demultiplexing from/to a maximum of 30 subports per port. Althou gh our current implementation of the architecture is targeted primaril y to ATM, the principles behind the architecture are more general, and apply to IP switching and routing technologies.