A 2.488-GBIT S SILICON BIPOLAR CLOCK AND DATA RECOVERY CIRCUIT FOR SONET FIBEROPTIC COMMUNICATIONS NETWORKS/

Adjustment-free clock and data recovery for 2.488-Gbit/s SONET applica tions is provided by a 1.77W, 3.45 x 3.45-mm(2) chip implemented in a 25-GHz f(T) silicon bipolar process. The chip has an on-chip VCO and o perates from 2 to 3 Gbits/s over process, voltage, and temperature var iations with a single off-chip filter capacitor. For network monitorin g, a highly reliable loss-of-signal detector is provided. For good mec hanical, thermal, and RF performance, a custom package was developed u sing HP's fine-line hybrid process.