A MODULAR ARCHITECTURE FOR A 6.4-GBYTE S, 8-MB DRAM-INTEGRATED MEDIA CHIP/

A modular architecture for a DRAM-integrated, multimedia chip with a d ata transfer rate of 6 to 12 Gbyte/s is proposed, The architecture off ers the design flexibility in terms of both DRAM capacity and the logi c-memory interface for use in a wide variety of applications, A DRAM m acro built from cascadable DRAM bank modules having a 256-kb memory ca pacity and 128-b I/O's provides flexibility and reconfigurablity of DR AM capacity and a high data transfer rate with an area of 6.4 mm(2)/Mb , A data transfer circuit (called the ''reconfigurable data I/O attach ment''), which is attached to the I/O lines of the DRAM macro, provide s a flexible logic-memory interface by changing the data-transfer rout es between the DRAM macro and logic circuits in real time. A 6,4-Gbyte /s test chip (called the ''media chip'') for three-dimensional compute r graphics was fabricated to test the proposed design methodology, It integrates an 8-Mb DRAM and four pixel processors on an 8.35 x 14.6-mm chip by using a 0.4-mu m CMOS design rule.