LOW-VOLTAGE, HIGH-SPEED CIRCUIT DESIGNS FOR GIGABIT DRAMS

This paper describes several new circuit design techniques for low V-C C regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (Delta V-BL) as well as the V -GS margin by boosting the sensing node voltage with a voltage depende nt boosting capacitor and 2) an I/O current sense amplifier with a hig h gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation schem e. An experimental 16 Mb DRAM chip with tile 0.18-mu m twin-well, trip le-metal CMOS process has been fabricated, and an access time from the row address strobe (t(RAC)) of 28 ns at V-CC = 1.5 V and T = 25 degre es C has been obtained.