H. Hirano et al., 2-V 100-NS 1T/1C NONVOLATILE FERROELECTRIC MEMORY ARCHITECTURE WITH BITLINE-DRIVEN READ SCHEME AND NONRELAXATION REFERENCE CELL/, IEEE journal of solid-state circuits, 32(5), 1997, pp. 649-654
Nonvolatile memory embedded in microcontrollers has required a 100 ns
access time at 2.0 V for mobile information terminals operating with a
rechargeable battery, To achieve this, this paper proposes a new ferr
oelectric nonvolatile memory (FeRAM) architecture that utilizes a bitl
ine-driven read scheme and a nonrelaxation reference cell for high-spe
ed and low-voltage operations, respectively, Using this architecture,
FeRAM with a one transistor and one capacitor per bit (1T/1C) cell can
achieve 100 ns access time at 2.0 V.