A COMPACT ON-CHIP ECC FOR LOW-COST FLASH MEMORIES

A compact on-chip error correcting circuit (ECC) for low cost Flash me mories has been developed,The total increase in chip area is 2%, inclu ding all cells, sense amplifiers, logic, and wiring associated with th e ECC, The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND Flash memor y, The cumulative sector error rate has been improved from 10(-1) to 1 0(-10). By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the convent ional ECC and occupy a large part of tile ECC area, have been eliminat ed, As a result, the area for the circuit has been drastically reduced by a factor of 25, The proposed on-chip ECC has been optimized in con sideration of balance between the reliability improvement and the cell area overhead, The power increase has been suppressed to less than 1 mA.