A 960-MB S/PIN INTERFACE FOR SKEW-TOLERANT BUS USING LOW JITTER PLL/

This paper describes an I/O scheme for use in a highspeed bus which el iminates setup and hold time requirements between clock and data by us ing an oversampling method, The I/O circuit uses a low jitter phase-lo cked loop (PLL) which suppresses the effect of supply noise, Measured results show peak-to-peak jitter of 150 ps and rms jitter of 15.7 ps o n the clock line, Two experimental chips with 4-pin interface have bee n fabricated with a 0.6-mu m CMOS technology, which exhibits the bandw idth of 960 Mb/s per pin.