A mixed-signal RAM decision-feedback equalizer (DFE) that operates at
90 Mb/s is described, In the analog domain, the DFE subtracts intersym
bol interference caused by the past four outputs, The equalized signal
is fed into a nonuniform flash analog-to-digital converter (ADC) to p
roduce the decision output and error signal used to adapt the RAM cont
ents in the digital domain, With a 5-V supply voltage, the power dissi
pation is 260 mW during steady-state operation, The active area is 4.5
mm(2) in a 1-mu m CMOS process.