A 2-GHZ 1.6-MW PHASE-LOCKED LOOP

This paper describes the design of a 2-GHz 1.6-mW phase-locked loop (P LL) fabricated in an 18-GHz 0.6-mu m BiCMOS technology, Employing cros s-coupled delay-elements and inductive peaking, the circuit merges the oscillator and the mixer into one stage to lower the power dissipatio n. An experimental prototype exhibits an rms jitter of 2.8 ps, a track ing range of 100 MHz, and a capture range of 70 MHz while operating fr om a 3-V supply, The phase noise in the locked condition is -115 dBc/H z at 400 kHz offset.