THE MASTER FRAMEWORK

The MASTER Framework has a two-level architecture. The first level con sists of a standard structure format and a set of MASTER Tools'. This provides a high quality, utility-based framework that supports highly interactive use. The second level is a 'Virtual Wafer Fab' that adds c apabilities for large-scale simulation-based design and experimentatio n. Powerful semiconductor technology CAD systems are constructed by po pulating the MASTER Framework with conforming process and device simul ators.