CHIP DESIGN FOR MONOBIT RECEIVER

A design for the monobit-receiver application-specific integrated circ uit (ASIC) will be described, The monobit receiver is a wide-band (1-G Hz) digital receiver designed for electronic-warfare applications, The receiver can process two simultaneous signals and has the potential f or fabrication on a single multichip module (MCM). The receiver consis ts of three major elements: a nonlinear RF front end, a signal sampler and formatting system (analog-to-digital converter (ADC) and demultip lexers), and a patented ''monobit'' algorithm implemented as an ASIC f or signal detection and frequency measurement, The receiver's front en d, ADC, and algorithm experimental performance results were previously presented [1], The receiver uses a 2-b ADC operating at 2.5 GHz whose outputs are collected and formatted by demultiplexers for presentatio n to the ASIC, The ASIC has two basic functions: to perform a fast Fou rier transform (FFT) and to determine the number of signals and report their frequencies, The ASIC design contains five stages: the input, t he FFT, the initial sort, the squaring and addition, and the final sor t. The chip will process the ADC outputs in real time, reporting detec ted signal frequencies every 102.4 ns.