A PHASE ASSIGNMENT METHOD FOR VIRTUAL-WIRE-BASED HARDWARE EMULATION

In a hardware emulator consisting of multiple field-programmable gate arrays (FPGA's), the utilization of the FPGA logic resource is usually very low due to the limitation on the number of I/O pins, Virtual wir e technology not only increases the inter-FPGA communication capabilit y, but it also increases the logic resource utilization by means of ti me division multiplexing (TDM). TDM allows one physical wire to be sha red by multiple logical wires. For TDM to be effective, each transport ation of an inter-FPGA signal must be carefully assigned to a slot of the time division. In this note, we show that the phase assignment pro blem is exactly same as the resource-constrained operation scheduling problem. We adopt the static-list scheduling heuristic for the task, a nd present some experimental results on a set of benchmark circuits fr om the MCNC. The experiments show that the proposed method can increas e the number of effective I/O pins as many as ten times.