LOGIC SYNTHESIS OF MULTILEVEL CIRCUITS WITH CONCURRENT ERROR-DETECTION

This paper presents a procedure for synthesizing multilevel circuits w ith concurrent error detection, All errors caused by single stuck-at f aults are detected using a parity-check code, The synthesis procedure (implemented in Stanford CRC's TOPS synthesis system) fully automates the design process, and reduces the cost of concurrent error detection compared with previous methods. An algorithm for selecting a good par ity-check code for encoding the circuit outputs is described. Once the code has been selected, a new procedure called structure-constrained logic optimization is used to minimize the area of the circuit as much as possible while still using a circuit structure that ensures that s ingle stuck-at faults cannot produce undetected errors, It is proven t hat the resulting implementation is path fault secure, and when augmen ted by a checker, forms a self-checking circuit. The actual layout are as required for self-checking implementations of benchmark circuits ge nerated with the techniques described in this paper are compared with implementations using Berger codes, single-bit parity, and duplicate-a nd-compare. Results indicate that the self-checking multilevel circuit s generated with the procedure described here are significantly more e conomical.