AIR-GAP FORMATION DURING IMD DEPOSITION TO LOWER INTERCONNECT CAPACITANCE

The use of air-gaps between interconnect metal lints to reduce interco nnect capacitance has been explored, Simulations were performed to det ermine the reduction in capacitance obtainable using air-gaps. The for mation of air-gaps in the isolation oxide between metal lines was simu lated using Stanford Profile Emulator for Etching and Deposition in IC Engineering (SPEEDIE), The capacitance of the SPEEDIE profiles was th en extracted using Raphael (an electrical analysis simulator from TMA) . The feasibility of air-gaps was also demonstrated experimentally. Fa bricated air-gap structures exhibited a 40% reduction in capacitance w hen compared to a HDP-CVD oxide gap-fill process with K = 4.1. Additio nally, the air-gap structures did not exhibit any appreciable leakage current.