A 100 MIPS HIGH-SPEED AND LOW-POWER DIGITAL SIGNAL PROCESSOR

A 100 MIPS high speed and low power fixed point Digital Signal Process or (DSP) has been developed applying 0.45 mu m CMOS TLM technology. Th e DSP contains a 16-bit X32K full CMOS static RAM with a hierarchical low power architecture. The device is a RAM based DSP with a total of 4.2 million transistors and a new low power design and process which e nabled an approximate 50% reduction in power as compared to convention al DSPs at 40 MHz. In order to cover very wide application requirement s, this DSP is capable of operating at 1.0 V [1] for DSP core and 3.3 V for I/O. This was achieved by new level shifter circuitry to interfa ce with cost effective 3 V external commodity products and confirmed 8 0% of power reduction at Core_V-DD=2.0 V, I/O_V-DD=3.3 V at 40 MHz. Th is paper describes the new features of the high speed and low power DS P.