A 0.18-MU-M CMOS HOT-STANDBY PLL USING A NOISE-IMMUNE ADAPTIVE-GAIN VCO

Phase-Locked Loop (PLL) designers have two major problems with regard to the production of practical, portable multimedia communication syst ems. The first is the difficulty of achieving both fast lock time and low jitter operation simultaneously. This can be particularly difficul t because the increase in loop stability needed to reduce jitter incre ases the lock time. The second is the problem caused by circuits opera ting at low voltage supplies. Low voltage supplies adversely effect th e performance of phase-frequency detectors and charge pump circuits, a nd they can decrease the noise immunity of oscillators. We have develo ped a hot-standby architecture, which can achieve both fast lock time and low jitter operation simultaneously, and low-voltage circuit techn iques, such as a noise-immune adaptive-gain voltage-controlled oscilla tor, for a fabricated PLL. This PLL is fully integrated onto a 480-mu m x 450-mu m die area with 0.18-mu m CMOS technology. II can operate f rom 0.5 V to 1.2 V, and with a lock range from 40 MHz to 170 MHz at 0. 5 V. The jitter is less than 200 ps and the lock time is less than 500 ns.