A LOW-POWER DATA-STORAGE CIRCUIT WITH AN INTERMITTENT POWER-SUPPLY SCHEME FOR SUB-1 V MT-CMOS LSIS

An experimental latch circuit is fabricated by using a 0.35 mu m MT-CM OS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 1 0% over those of a conventional MT-CMOS circuit. Furthermore, at a ope ration frequency of 100 MHz, an SRAM employing this IFS scheme has a s tandby current which is 0.4% of SRAM's without using IPS scheme.