A CAD-BASED LOW-POWER DESIGN METHODOLOGY FOR VERY HIGH-SPEED SI BIPOLAR STANDARD CELL LSIS

A computer-aided low-power design methodology for very high-speed Si b ipolar standard cell LSI is described. In order to obtain Gbit/s-speed operation, it features a pair of differential clock channels inside c ells and a highly accurate static timing analysis for back annotation. A newly developed CAD-based power optimization scheme minimizes cell currents while maintaining circuit speed. A 5.6k gate SDH signal-proce ssing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption de monstrates the effectiveness of this design technology.