THE MOST ESSENTIAL FACTOR FOR HIGH-SPEED, LOW-POWER 0.35 MU-M COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR CIRCUITS FABRICATED ON SEPARATION-BY-IMPLANTED-OXYGEN (SIMOX) SUBSTRATES

We present experimental data concerning the propagation delay time and the power consumption of 0.35 mu m complementary metal-oxide-semicond uctor (CMOS) gates (inverter, NAND, NOR) fabricated on the commercial standard high dose separation-by-implanted-oxygen (SIMOX) substrates. Each CMOS gate was composed of the fully depleted (FD) mode N- and P-t ype metal-oxide-semiconductor (NMOS and PMOS) transistors or the parti ally depleted (PD) mode ones with no body-contact. On the basis of the experimental data, together with SPICE simulation results, we show th at the FD-mode is not the primary factor for high-speed, low-power per formances of the CMOS/SIMOX circuits, but the reduced drain parasitic capacitance (both the bottom and the peripheral components) with the t hin film silicon-on-insulator (SOI) structure is. Furthermore, we show the. significance of the design and control of the transistor thresho ld voltage and/or the off-state leakage current for high-speed, low-po wer CMOS/SIMOX circuits.