PERFORMANCE OF SINGLE-ELECTRON TRANSISTOR LOGIC COMPOSED OF MULTI-GATE SINGLE-ELECTRON TRANSISTORS

We have performed Monte Carlo studies of complementary capacitively co upled single-electron transistor (complementary C-SET) logic gates for single-electron digital logic circuits. The simulations carried out w ith various types of complementary C-SET logic gates showed that seria l connections of single-electron transistors necessary for multi-input operations resulted in the degradation of the switching speed. It is pointed out that the multi-gate single-electron transistor configurati on can provide a possible means to circumvent this problem. However, t he associated nonsymmetric input-output characteristics could cause th e operation failure of the circuit. It is shown that the multi-gate si ngle-electron transistor circuits are the optimal choice from the stan dpoint of high speed operation and design simplicity, when confined to the input voltages not exceeding four terminals.