This paper describes an analog-to-digital converter which combines mul
tiple delta-sigma modulators in parallel so that time oversampling may
be reduced or even eliminated, By doubling the number of Lth-order de
lta-sigma modulators, the resolution of this architecture is increased
by approximately L bits, Thus, the resolution obtained by combining n
d delta-sigma modulators in parallel with no oversampling is similar t
o operating the same modulator with an oversampling rate of M. A paral
lel delta-sigma A/D converter implementation composed of two, four, an
d eight second-order delta-sigma modulators is described that does not
require oversampling, Using this prototype, the design issues of the
parallel delta-sigma A/D converter are explored and the theoretical pe
rformance With no oversampling and with low oversampling is verified,
This architecture shows promise for obtaining high speed and resolutio
n conversion since it retains much of the insensitivity to nonideal ci
rcuit behavior characteristic of the individual delta-sigma modulators
.