A 110-K TRANSISTOR 25-MPIXELS S CONFIGURABLE IMAGE TRANSFORM PROCESSOR UNIT/

A configurable architecture for performing image transform algorithms is presented that provides a better tradeoff between low complexity an d algorithm flexibility than either software-programmable processors o r dedicated ASIC's. The configurable processor unit requires only 110 K transistors and can execute several image transform algorithms. By e mulating the signal how of the algorithms in hardware, rather than sof tware, complexity is reduced by an order of magnitude compared with cu rrent software programmable video signal processors, while providing m ore flexibility than single function ASIC's, The processor has been fa bricated in 1.2-mu m CMOS and has been successfully used to execute th e discrete cosine transform/inverse discrete cosine transform (DCT/IDC T), subband coding, vector quantization, and two-dimensional filtering algorithms at pixel fates up to 25 MPixels/s.