A BICMOS FRONT-END SYSTEM WITH BINARY DELAY-LINE FOR CAPACITIVE DETECTOR READ-OUT

As part of the entire readout chip, a low-power high-gain transresista nce amplifier has been developed, followed by a high-speed, low-power small offset comparator and a binary delay line, The amplifier is bala nced, fully differential in circuit topology, and symmetrical in layou t, making it radiation tolerant and relatively insensitive to varying magnetic fields, Also, the comparator is fully symmetrical with a bala nced input stage, Before irradiation (Pre-rad) the transresistance amp lifier has a measured differential gain of 110 mV/4 fC, an average 10/ 90% rise time (t(10/90%)) of 20 to 50 ns depending on the bias conditi ons, a noise figure of 433 circle plus 93(C-t)(1.08) (where the symbol circle plus stands for root()(2)+()(2)) electrons (e(-)), and a power consumption of 750 mu W. The comparator uses bipolar transistors in t he regenerative stage resulting in a small offset, a sensitivity <1.5 mV, and a power consumption of approximate to 350 mu W at 40 MHz. The maximum pre-rad frequency at which the comparator is still functioning correctly is approximate to 100 MHz. Pre-rad, the binary delay line h as a delay of 2.1 mu s at 40 MHz and a power consumption of approximat e to 350 mu W/channel for a four-channel design, The complete readout channel-amplifier, comparator, and binary delay line-consumes approxim ate to 1.5 mW. The entire readout system was implemented in the radiat ion-hard 0.8-mu m SOI-SIMOX BiCMOS-PJFET technology of DMILL.