HIGH-SPEED, LOW-POWER BICMOS COMPARATOR USING A PMOS VARIABLE LOAD

A novel BICMOS latched comparator for high-speed, low-power applicatio ns is proposed, The resistive load of conventional current-steering co mparators is replaced by a variable load made by a pMOS transistor tha t, during the comparison cycle, is successively biased in three differ ent operating regions, This solution provides a lower power consumptio n than conventional architectures, without sacrificing sampling speed. Post-layout simulation results and measurements performed on the prot otypes are presented.