OPTIMIZING MOS-TRANSISTOR MISMATCH

Authors
LOVETT SJ WELTEN M MATHEWSON A MASON B
Citation
Sj. Lovett et al., OPTIMIZING MOS-TRANSISTOR MISMATCH, IEEE journal of solid-state circuits, 33(1), 1998, pp. 147-150
Citations number
10
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
33
Issue
1
Year of publication
1998
Pages
147 - 150
Database
ISI
SICI code
0018-9200(1998)33:1<147:OMM>2.0.ZU;2-7
Abstract
An investigation of MOS transistor mismatch is undertaken and a method ology is developed for optimizing mis-match without increasing layout area. Dramatic improvements of up to 300% in matching can be realized by selecting the optimum W/L ratio without changing the overall WL are a product, The theoretical basis for the obtainable improvements is fu lly described and an expression is derived and verified by experiment to predict the W/L ratio which gives optimum matching.