IMPROVED ARCHITECTURES FOR THE ADD-COMPARE-SELECT OPERATION IN LONG CONSTRAINT LENGTH VITERBI DECODING

While turbo coding techniques have received much recent attention for their extraordinary coding gains, these techniques inherently suffer l atency limitations unacceptable in most telephony applications, Long c onstraint length (LCL) Viterbi decoding (VD) techniques hold promise f or significant coding gains at low latencies, This paper presents two novel architectures for the add-compare-select unit of an LCL VD. The derived bit-serial circuits are shown to be more efficient than tradit ional bit-serial methods with one solution 24% more efficient than tra ditional approaches and requiring only 1/2 the I/O. Using these techni ques, a hardware Viterbi decoder was designed, built, and tested.