DEEP-SUBMICRON CMOS TECHNOLOGIES FOR LOW-POWER AND HIGH-PERFORMANCE OPERATION

Integrated circuits with 1GHz logic, 1G bit DRAM, and 1G transistors, together with the CMOS technology with a gate length of less than 0.2 mu m are the ingredients of the ''Giga-Era.'' However, in order to int egrate these billions of MOSs at giga-frequencies, the problem of the power consumption cannot be avoided. It is a common practice to cope w ith this problem by reducing the power supply voltage. In deep submicr on MOS, although the basic gate delay is not likely to degrade as the power supply voltage is reduced, it is necessary to set a low threshol d value (V-th) within the wafer plane with reduced parasitic devices, if the absolute current values become important, as in the interconnec t load. However, reliability problems involving the short-channel effe ct and hot carriers then cannot be avoided. This paper describes the u se of the cobalt silicide process and shallow extension structure of t he source/drain to reduce the parasitic resistance. It is also shown t hat setting a low V-th with fewer fluctuations is possible by combinin g the double-side-wall process and the counter-dose process. By means of the above process, deep submicron CMOS with low parasitic resistanc e and low V-th can be fabricated.