MEMORY EFFICIENT PROGRAMMABLE PROCESSOR CHIP FOR INVERSE HAAR-TRANSFORM

In this correspondence, a processor chip programmable between N = 8 an d N = 1024 for the unidimensional inverse Haar transform (1-D-IFHT) is presented. The processor uses a low latency data-flow with an archite cture that minimizes the internal memory and an adder/subtracter as th e only computing element The control logic has a single and modular st ructure and can be easily extended to longer transforms. A prototype o f the 1-D-IFHT processor has been implemented using a standard-cell de sign methodology and a 1.0-mu m CMOS process on a 11.7 mm(2) die. The maximum data rate is close to 60 MHz.