A COMPACT MODEL FOR THE GROUNDED-GATE NMOS TRANSISTOR BEHAVIOR UNDER CDM ESD STRESS

The parasitic bipolar transistor inherent to grounded gate nMOS transi stors is modelled, accounting for the specific conditions applied by C DM ESD stress. The avalanching of both, drain and source, the triggeri ng of snapback and the CDM-specific bipolar saturation mode are addres sed. Furthermore, a fast analytical method to determine CDM ESD lumped tester parasitics from measured pulse characteristics is presented. T he triggering of the grounded gate nMOS transistor under CDM is studie d in detail for different gate lengths. The optimal gate length for CD M protection in advanced submicron technologies is discussed. (C) 1998 Elsevier Science B.V.