AN EVALUATION OF BIPARTITIONING TECHNIQUES

Logic partitioning is an important issue in VLSI CAD, and has been an area of active research for at least the last 25 years, Numerous appro aches have been developed and many different techniques have been comb ined for a wide range of applications. In this paper, we examine many of the existing techniques for logic bipartitioning and present a meth odology for determining the best mix of approaches, The result is a no vel bipartitioning algorithm that includes both new and preexisting te chniques. Our algorithm produces results that are at least 16% better than the state of the art while also being efficient in run time.