DAMASCENE COPPER INTERCONNECTS WITH POLYMER ILDS

On-chip interconnects with copper metallization and polymer interlevel dielectrics (ILDs) have the lowest R-C delay, lowest parasitic coupli ng and highest electromigration resistance of currently proposed room temperature material sets. Patterning of such interconnect structures requires either damascene patterning (chemical-mechanical planarizatio n (CMP) of copper deposited into trenches and via reactive ion etching (RIE) into the polymer) or elevated temperature RIE patterning of the copper. In this paper we present the dual damascene patterning of cop per on low dielectric constant polymers like divinylsiloxane bisbenzoc yclobutene (DVS bis BCB) and parylene-n. In particular, we present and discuss various RIE polymer etch masks and CMP polish stops that have been utilized in this work (such as PECVD silicon nitride, PECVD sili con dioxide and tantalum) and the results with different pads and slur ries. Emphasis is placed on achieving a planar copper CMP with a minim um amount of polish stop and polymer ILD erosion, as well as attaining low contact resistance. Difficulties in achieving these desirable fea tures with relatively soft low dielectric constant polymers are presen ted, with contact resistivity in the mid 10(-9) Ohm-cm(2) having been achieved to date. (C) 1997 Elsevier Science S.A.