ALGORITHM-BASED FAULT-TOLERANCE - A REVIEW

Authors
Citation
M. Vijay et R. Mittal, ALGORITHM-BASED FAULT-TOLERANCE - A REVIEW, Microprocessors and microsystems, 21(3), 1997, pp. 151-161
Citations number
33
ISSN journal
01419331
Volume
21
Issue
3
Year of publication
1997
Pages
151 - 161
Database
ISI
SICI code
0141-9331(1997)21:3<151:AF-AR>2.0.ZU;2-4
Abstract
The need for reliability of computers has been increasing, as computer s have been put to use in more and more practical applications. Multip rocessor architectures have provided elegant solutions for certain com putationally expensive problems which find wide-ranging applications i n areas such as defense and industry. Since computer-intensive applica tions are run on these architectures, the probability that some comput ations will incur error is not negligible. Hence fault tolerance plays an important role in the design of multiprocessor architectures. In t his paper, we review a low-cost scheme for adding fault tolerance in m ultiprocessor architectures, called algorithm-based fault tolerance (A BFT). The concurrent error detecting and correcting capabilities of th is scheme are demonstrated with the help of examples. Various issues o f interest, the areas open to research and the limitations of ABFT are also pointed out. (C) 1997 Elsevier Science B.V.