NOISE SUPPRESSION SCHEME FOR GIGABIT-SCALE AND GIGABYTE S DATA-RATE LSIS/

In order to reduce the power/ground noise due to the off-chip parasiti c inductance and realize gigabit-scale and ultra-high bandwidth large scale integrations (LSI's), this paper proposes two new techniques: 1) a constant-current voltage-down converter (VDC) which reduces the dif ferential mode noise caused by internal peak current in a chip, and 2) a partially inverted data bus architecture which suppresses the commo n-mode noise caused by driving a large amount of output buffers, The n ew VDC requires almost constant current through an external V-dd/V-ss pin in spite of an internal large peak current, resulting in the suppr ession of the inductance induced voltage bounce and oscillation, Using the new VDC, the power/ground noise in a l-Gb DRAM is reduced to 20% of the conventional one. The new bus architecture reduces the common-m ode noise to 1/n by inverting output bus data partially, using only n- 1 bit flag signals, Moreover, the modified new bus architecture reduce s the noise to 1/2n by using only n bit flag signals. These architectu res achieve the ultra-high data transfer rate of 16 GB/s to 32 GB/s.