A BICMOS IMPLEMENTATION OF A 276MS S FORWARD EQUALIZER AND 200MS/S FDTS DETECTOR/

An analog finite impulse response filter (FIR) and an analog fixed del ay tree search (FDTS) tau=1 detector suitable for disk drive applicati ons are presented, The FIR uses a rotary architecture with interleaved operation which allows clock rates up to 276MS/s to be used, The FIR has seven taps, all programmable to six bit weights, and is implemente d in fully differential form, The detector operates with clock rates u p to 200MS/s with no code restrictions. It makes use of a reduced mini mum mean square error equation set to simplify the detector, Dual feed back filters are also used to shorten the critical path, A seven tap f eedback filter is used with six bits of resolution per tap. The FIR co nsumes 180 mW while the detector uses 270 mW. The die size including a ll test buffers for the FIR and detector is 5.2 mm(2).