HIGH-PERFORMANCE FPGA-BASED IMPLEMENTATION OF KALMAN FILTER

An FPGA-based fully hardware Kalman filter has been designed and prese nted and a reconfigurable Kalman filter-based coprocessor in FPGAs has been proposed. High-speed arithmetic function implementations and pip elining have been used and a substantial improvement in performance ha s been gained. The cycle time (one iteration) for computing Kalman fil ter is reduced from 1.8274 mu s in our previous design to 0.4013 mu s. The performance gained in our approach includes two to four orders of magnitude higher speed than other implementations. The high-speed, re congifuration and easy-to-develop characteristics of the FPGA-based Ka lman filter will largely broaden the real-time application area of Kal man filter. (C) 1997 Elsevier Science B.V.