FAILURE ANALYSIS OF VLSI BY I-DDQ TESTING

A method for enhancing the popular failure techniques has been present ed. The method was built on three principles: CMOS devices only draw p ower during switching operation; fault defects, both Boating and stuck will consume power if properly conditioned; bridging fault model test programs combined with the combinational logic designs, the elevated power state should surface at some vector point prior to the location of the falling vector. A system was constructed by making use of an ol der vintage emission microscope. The system was configured so that dir ect docking to existing production hardware is possible. Using this sy stem, five case studies were presented. The case studies proved that q uiescent current signature scan analysis was successful at locating th e defects within the failing units after conventional failure analysis techniques had been exhausted. Both bridging faults and floating faul ts were detected.