FAULT-TOLERANT MESHES WITH EFFICIENT LAYOUTS

Authors
YAMADA T UENO S
Citation
T. Yamada et S. Ueno, FAULT-TOLERANT MESHES WITH EFFICIENT LAYOUTS, IEICE transactions on information and systems, E81D(1), 1998, pp. 56-65
Citations number
15
Categorie Soggetti
Computer Science Information Systems
Journal title
IEICE transactions on information and systems → ACNP
ISSN journal
09168532
Volume
E81D
Issue
1
Year of publication
1998
Pages
56 - 65
Database
ISI
SICI code
0916-8532(1998)E81D:1<56:FMWEL>2.0.ZU;2-U
Abstract
This paper presents a practical fault-tolerant architecture for mesh p arallel machines that has t spare processors and has 2(t + 2) communic ation links per processor while tolerating: at most t + 1 processor an d link faults. We also show that the architecture presented here can b e laid out efficiently in a linear area with wire length at most O(roo t t).