AN IF-BAND MMIC CHIP SET FOR HIGH-SPEED WIRELESS COMMUNICATION-SYSTEMS

This paper proposes a set of three IF-band MMICs for high-speed wirele ss communication systems. The first of the circuits in this chip set i s an MMIC logarithmic limiting receiver amplifier. This amplifier util izes the self-phase distortion compensation technique, combining a com mon-source FET and a common-drain FET, to reduce phase distortion. The limiting characteristics were gain of more than 65 dB, 2.2-dBm satura ted output power and phase deviation of less than 5 degrees. A logarit hmic accuracy of 2 dB and RSSI change coefficient of more than 11 mV/d B were also achieved. Typical power consumption was less than 0.58 W w ith the supply voltages of +3 V and -2 V. The second of the fabricated circuits is an MMIC transmitter amplifier with more than 24-dB gain a t 140 MHz. And the third of the fabricated circuits is an MMIC 90 degr ees signal divider and combiner. This MMIC combines a set of amplifier s with a set of dividers having a constant phase difference of 90 degr ees. Thus the isolation between the transmission port and the receptio n port is obtained. The chip size is less than 1/100 that of a commerc ial 140-MHz-band 90 degrees coupler. At the frequency of 140 MHz, the mean transmission loss is about 2.1 dB for the divider parr and 3.0 dB for the combiner part. Furthermore, in the frequency range of 130 MHz to 150 MHz, signal leakage from the transmission port to the receptio n port is suppressed by more than 24 dB.