NEW SCAN DESIGN WITH SCANNABLE MEMORY ARRAYS

Scan design has been popular as a design-for-testability technique for sequential circuits. Embedded memory arrays such as register files, h owever, have been regarded as non-scannable. This paper proposes new s can design which makes memory arrays scannable by adding a small auxil iary circuit including a counter and multiplexers. It allows plural me mory arrays to be chained into a single scan path along with ordinary flip-flops. Thus the scan path approach expands its application area t o sequential circuits including both ordinary flip-flops and memory ar rays. It features a memory array test during scan operation, ease in m emory array failure analysis, and automatic test pattern generation wi thout making any distinction between flip-flops and memory arrays. We discuss the scan method, scannable memory array configuration, and imp lementation and evaluation of the scannable CMOS and bipolar LCML (Low Energy Current Mode Logic) register file macros.