SCAN DESIGN METHODOLOGY FOR LARGE-SCALE ASICS

Scan design has been widely used as a design-for-testability technique , and full-scan design can generally achieve a high fault coverage. It s application to large-scale ASICs, however, has caused several proble ms such as lack of sufficient design support system, increasing scan d esign overheads, and difficulty in achieving high quality design. To o vercome these problems, we developed a scan design methodology that au tomatically networks scan elements in a circuit, improves routability by reordering scan elements, compensates timing of scan operation afte r reordering, and verifies scan operation. The methodology enables us to design large-scale ASICs without scan design errors and with low ha rdware overheads; because the scan path is automatically generated and sufficiently verified, and scan path reordering makes routability hig her, and timing compensation reduces delay gate insertion for timing a djustment. We have applied this methodology to more than 100 ASICs var ying from 40,000 to 340,000 gates for supercomputer SX-4, PX7800/7900 mainframes, and NX series UNIX server. Using this methodology, we redu ced the hardware overheads to less than 10%, achieved high quality des ign by sufficient verification, and obtained a fault coverage of more than 95%. As a result, we successfully tested the ASICs from the first lot and got high quality ASICs.