COMPACT REALIZATION OF PHASE-LOCKED LOOP USING DIGITAL-CONTROL

This paper describes a phase-locked loop (PLL) with digital control fe aturing a binary quantizing circuit, a synchronizing algorithm, a lock detector and a compact D/A converter. The binary quantizing circuit a nd synchronizing algorithm make it possible to compare phase and frequ ency together and to reduce digital control logic by half. Interpolati on of upper-bit D/A converter output by lower-bit output reduces the n umber of current sources of a 9 bit D/A converter from 511 to 80. SPIC E simulation with a 0.25 mu m CMOS has demonstrated that the developme nt of 200 MHz PLL using digital control is feasible.