HIERARCHICAL WORD-LINE ARCHITECTURE FOR LARGE-CAPACITY DRAMS

The number of DRAMs that have adopted hierarchical word-line architect ure has increased as developed DRAM memory capacity has increased to m ore than 64 Mb. Use of the architecture enhances many kinds of DRAM pe rformances, such as access time and fabrication process margin. Howeve r, the architecture does cause some problems. This paper describes som e kinds of hierarchical word-line circuitries that have been proposed. It also describes a partial subarray activation scheme that is combin ed with hierarchical word-line and data-line architectures and discuss es their potential and required specifications for future multi-giga b it DRAMs.