K. Furutani et al., A BOARD-LEVEL PARALLEL TEST CIRCUIT AND A SHORT-CIRCUIT FAILURE REPAIR CIRCUIT FOR HIGH-DENSITY, LOW-POWER DRAMS, IEICE transactions on electronics, E80C(4), 1997, pp. 582-589
This paper proposes a new test mode circuit which enables the massivel
y parallel test of DRAMs with a standard LSI tester with little chip a
rea penalty. It is useful to enhance the test throughput that can't be
improved by the conventional multi-bit test mode. And a new redundanc
y circuit that detects and repairs the short circuit failures in the m
emory cell array is also proposed. It greatly improves the yield of su
per low power 256 Mbit DRAMs.