A 6.93-MU-M(2) FULL CMOS SRAM CELL TECHNOLOGY FOR 1.8-V HIGH-PERFORMANCE CACHE MEMORY

A high-performance microprocessor-compatible small size full CMOS SRAM cell technology for under 1.8-V operation has been developed. Less th an 1-mu m spacing between the n and pMOSFETs is achieved by using a re trograde well combined with SSS-OSELO technology. To connect the gates of a driver nMOSFET and a load pMOSFET directly, a 0.3-mu m n-gate lo ad pMOSFET, formed by amorphous-Si-film through-channel implantation, is merged with a 0.25-mu m p-gate pMOSFET for the peripheral circuits. The memory cell area is reduced by using a mask-free contact process for the local interconnect, which includes titanium-nitride wet-etchin g using a plasma-TEOS silicone-dioxide mask. The newly developed memor y cell was demonstrated using 0.25-mu m CMOS process technology. A 6.9 3-mu m(2) and 1-V operation full CMOS SRAM cell with a high-performanc e circuit was achieved by a simple fabrication process.