Ie. Opris, RAIL-TO-RAIL MULTIPLE-INPUT MIN MAX CIRCUIT, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 45(1), 1998, pp. 137-140
This brief presents a multiple-input min/max circuit technique that re
duces the errors associated with previous analog implementations by co
mbining a common-source voltage-mode configuration with a current-mode
''winner takes all'' circuit. The overall architecture exhibits linea
r complexity with the number of inputs. Both minimum and maximum two-i
nput prototypes have been designed and built in a 2-mu m CMOS process.
The active area for each circuit is 650 x 100 mu m(2), and the total
power dissipation is 0.8 mW from a single 5-V supply. Experimental res
ults confirm rail-to-rail operation and sharp transition regions.