METHODOLOGIES FOR TOLERATING CELL AND INTERCONNECT FAULTS IN FPGAS

The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occur rences of defects and operational faults. Thus, there is a critical ne ed for fault tolerance and reconfiguration techniques for FPGAs to inc rease chip yields (with factory reconfiguration) and/or system reliabi lity (with field reconfiguration). We first propose techniques utilizi ng the principle of node-covering to tolerate logic or cell faults in SRAM-based FPGAs. A routing discipline is developed that allows each c ell to cover-to be able to replace-its neighbor in a row. Techniques a re also proposed for tolerating wiring faults by means of replacement with spare portions. The replaceable portions can be individual segmen ts, or else sets of segments, called ''grids.'' Fault detection in the FPGAs is accomplished by separate testing, either at the factory or b y the user. If reconfiguration around faulty cells and wiring is perfo rmed at the factory (with laser-burned fuses, for example), it is comp letely transparent to the user. In other words, user configuration dat a loaded into the SRAM remains the same, independent of whether the ch ip is defect-free or whether it has been reconfigured around defective cells or wiring-a major advantage for hardware vendors who design and sell FPGA-based logic (e.g., glue logic in microcontrollers, video ca rds, DSP cards) in production-scale quantities. Compared to other tech niques for fault tolerance in FPGAs, our methods are shown to provide significantly greater yield improvement, and a 35 percent non-FT chip yield for a 16 x 16 FPGA is more than doubled.