A NOVEL-APPROACH TO RANDOM PATTERN TESTING OF SEQUENTIAL-CIRCUITS

Random pattern testing methods are known to result in poor fault cover age for most sequential circuits unless costly circuit modifications a re made. In this paper, we propose a novel approach to improve the ran dom pattern testability of sequential circuits. We introduce the conce pt of holding signals at primary inputs and scan flip-flops of a parti ally scanned sequential circuit for a certain length of time, instead of applying a new random vector at each clock cycle. When a random vec tor is held at the primary inputs of the circuit under test or at the scan flip-flops, the system clock is applied and the primary outputs o f the circuit are observed. Information obtained from a testability an alysis or test generator is used to determine the number of clock cycl es for which each random vector is to be held constant. The method is low cost and the results of our experiment on the benchmark circuits s how that it is very effective in providing fault coverage close to the maximum obtainable fault coverage using random patterns with full sca n.