ENHANCED DESIGN FOR FLIP-CHIP INTERCONNECTS

Multichip and flip chip technology has become increasingly popular in the past years. It employs a series of chips flipped and connected thr ough metallic bumps. A study for improving the performance of flip chi p interconnects is recently presented by Ghouz and El-Sharawy for freq uencies up to 50 GHz. In that study, the idea of staggering the signal line interconnect with respect to the ground plane bumps to reduce re flection and insertion loss is introduced. In this paper concentration is put on re-shaping the discontinuity region in order to provide a b etter impedance match between the CPW-motherboard and the CPW-chip, an d thus reducing reflection at the input terminals. Several approaches are tested to accomplish lower return loss, among them, the use of bum ps of different thickness located at different positions, the use of t ilted bumps or ''ramps'', and the use of dielectric loading on the bum ps. The results indicate that the performance of these Aip chips is gr eatly enhanced and extended to frequencies beyond 100 GHz.