EFFICIENT PROCESSOR ARRAYS FOR THE IMPLEMENTATION OF THE GENERALIZED PREDICTIVE-CONTROL ALGORITHM

Processor-array architectures for the efficient implementation of the generalised predictive-control (GPC) algorithm are introduced, each ex hibiting different area/time performance, processor utilisation and de gree of programmability. The special features that the partial algorit hms of GPC exhibit have been exploited, to derive efficient architectu res of low complexity. A remarkable reduction of the execution time re quired for a complete cycle of the algorithm is achieved, compared wit h the long delay of executing the algorithm on a single processor.