A reduction of the V-DD voltage, and thus the threshold voltage, in su
bmicrometre CMOS circuits, results in an increase in the subthreshold
current of the transistors and, consequently, in an increase in the ov
erall quiescent current. This effect prohibits the use of I-DDQ testin
g. Based on experimental investigation into the subthreshold character
istics of deep submicrometre transistors, the authors propose a coolin
g of the circuit under test as a method to reduce these difficulties.